Q
Hiring companyQualcomm
Verified 2 days ago
Staff Engineer, NPU/AI Processor Synthesis
Bangalore, Karnataka, India Full-time On-site
About the role
Hardware Engineering – ASIC Design team at Qualcomm focuses on delivering high‑performance silicon for next‑gen AI workloads. The Staff Engineer leads synthesis and timing closure for NPU IP, builds and optimizes scripts, and ensures PPA targets across advanced nodes. Works closely with RTL, architecture, and physical design teams on‑site in Bangalore, driving cross‑functional collaboration and mentoring junior engineers.
What you’ll do
- Lead RTL-to-gate synthesis for NPU IP and subsystems
- Develop and maintain synthesis scripts and hierarchical flows
- Drive pre- and post-layout timing closure across corners
- Apply physical-aware synthesis to meet aggressive PPA targets
- Validate and maintain SDC constraints and perform LEC checks
- Collaborate with RTL, DFT, and physical design teams for handoff
- Provide feedback to architecture for QoR improvements
- Explore advanced synthesis methodologies and tool capabilities
What you’ll bring
- 15+ years ASIC synthesis and timing closure experience
- 3+ years NPU or AI processor design
- Proficiency with Synopsys Design Compiler and Cadence Genus
- Expertise in STA tools such as PrimeTime
- Advanced Tcl, Perl, and Python scripting
- Low-power design using UPF/CPF flows
- Experience with advanced nodes (5nm/3nm)
- Mentoring junior engineers
Skills
ASIC synthesisTiming closureLow-power designTcl scriptingPython scriptingPhysical-aware synthesisSTA toolsMentorship
Education
Bachelor's/Master's/PhD in Electrical or Computer Engineering