Principal Engineer, Design Verification Engineering

About the role

Design Verification Engineering team at Analog Devices drives pre-silicon validation for next‑generation edge products. The Principal Engineer leads end‑to‑end SoC verification, defines strategies, architects UVM testbenches, and mentors a global verification team while collaborating with architecture, firmware and emulation groups. Bangalore, India, on‑site work model with occasional travel (≈10%).

What you’ll do

• Lead end‑to‑end SoC verification from planning to sign‑off
• Define and drive verification strategy and architecture
• Architect scalable UVM‑based testbenches and DV flows
• Collaborate with architecture and design teams on requirements
• Drive pre‑silicon readiness with emulation and FPGA teams
• Apply formal verification and coverage analysis across hierarchy
• Mentor and guide verification engineers
• Ensure functional and code coverage closure

What you’ll bring

• B.Tech/M.Tech degree
• 12+ years digital verification experience
• Expertise in SystemVerilog/UVM
• Power‑aware verification (UPF)
• Formal verification experience
• Proficiency in C/C++ and Python
• Knowledge of AI/ML accelerators
• Experience with high‑speed interfaces

Skills