Principal Design Engineer

About the role

Cadence Design Systems' Verification team builds robust verification environments for ASIC and SoC designs. The Principal Design Engineer leads strategy, architecture, and execution of DV projects, mentoring junior engineers and interfacing with design and architecture groups. Bangalore, India, on-site.

What you’ll do

• Define verification strategy and methodology
• Design scalable testbench architectures and BFMs
• Develop complex test cases and constrained-random stimuli
• Lead root-cause analysis and debug of design bugs
• Utilize formal verification to prove properties
• Monitor functional and code coverage metrics
• Oversee gate-level simulations for timing verification
• Mentor junior engineers and coordinate cross-functional teams

What you’ll bring

• 7-10 years DV experience
• Expertise in SystemVerilog and UVM
• Proficiency with Xcelium, VCS, Questa simulators
• Coverage-driven verification skills
• Formal verification tool experience
• Knowledge of AXI, AHB, APB, PCIe, DDR protocols
• Debugging with waveform tools like Verisium, SimVision
• Low-power verification (UPF/CPF)

Education

B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field