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Hiring companyCadence Design Systems
Verified today
Principal Design Engineer, Layout Design
Pune,India Full-time On-site
About the role
Cadence Layout Design Team builds cutting‑edge analog IP layouts for DDR IO and related circuits, delivering high‑performance designs in advanced 28nm and below nodes. The Principal Design Engineer leads custom layout efforts, performs physical verification (DRC/LVS), mentors a small engineering team, and collaborates closely with design and verification groups to ensure successful IP delivery. Pune, India, on‑site, Full‑time role with relocation assistance available.
What you’ll do
- Design custom analog layouts for DDR IO and related IP blocks
- Perform physical verification including DRC, LVS, and reliability checks, fixing violations
- Lead layout efforts and coordinate with design teams to meet specifications
- Mentor and guide a small team of engineers toward successful IP delivery
- Collaborate on layout techniques such as matching, shielding, and floorplan constraints
- Analyze layout impact on speed, capacitance, power, and area
- Utilize scripting/automation to streamline layout workflows
- Document designs and present results to internal and customer stakeholders
What you’ll bring
- 8-10 years of analog layout experience
- Hands‑on layout of analog IP such as op‑amps, bandgaps, data converters, LDOs, PLLs
- Experience with DDR IO layout and high‑speed analog (SerDes)
- Knowledge of DSM technology methodology and 28nm or smaller nodes
- Proficiency in layout verification (DRC/LVS) and reliability checks
- Scripting or automation skills (e.g., Python, TCL)
- Strong communication, documentation, and presentation abilities
- Ability to lead and mentor a small team of engineers
Skills
Analog layoutDDR IOPhysical verificationDRC/LVSDSM methodology28nm technologyScripting automationTeam leadership
Education
BE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent