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Hiring companyCadence Design Systems
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Principal Design Engineer
Hyderabad,India Full-time On-site
About the role
Cadence Design Systems' Analog Design team drives high‑speed interface IP development for Die‑to‑Die and chiplet systems. The Principal Design Engineer architects, designs, and validates analog/mixed‑signal circuits, collaborates with layout, verification, and advanced packaging groups, and leads silicon bring‑up and debug. Hyderabad, on‑site, hybrid schedule with occasional off‑site work as needed.
What you’ll do
- Architect and deliver high‑speed analog/mixed‑signal IPs for D2D and chiplet systems
- Define architecture, perform feasibility studies, and evaluate design trade‑offs for signal integrity and power
- Execute schematic design, simulation, and optimization using industry EDA tools
- Collaborate with layout, verification, and advanced packaging teams for co‑optimization
- Support layout reviews, parasitic extraction, and post‑layout sign‑off
- Lead silicon bring‑up, debug, and characterization activities
- Contribute to design methodology, checklists, and best practices
What you’ll bring
- 8+ years analog/mixed‑signal IC design
- Experience with high‑speed interfaces such as DDR, PCIe, SerDes, D2D links
- Strong knowledge of UCIe standard and chiplet architectures
- Proficiency in schematic design, simulation, and PVT corner analysis
- Understanding of advanced packaging impacts on high‑speed signaling
Skills
Analog circuit designHigh‑speed interface designUCIe standardAdvanced packagingSignal integrityPVT corner simulationSilicon bring‑upMentorship
Education
Bachelor's or Master's degree in Electrical/Electronics Engineering