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Hiring companyCadence Design Systems
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Senior Principal Design Engineer
Noida, IN, India Full-time On-site
About the role
Cadence Design Systems' semiconductor engineering team builds low‑power, high‑performance SRAM and register file circuits. The Senior Principal Design Engineer leads full‑custom and compiler‑based SRAM macro design, runs SPICE simulations, supervises layout, and validates silicon. Noida, India, on‑site work model.
What you’ll do
- Design and optimize full‑custom and compiler‑based SRAM macros
- Run SPICE simulations for timing, power, and SNM analysis
- Supervise physical design and layout teams
- Support post‑silicon validation and debugging
What you’ll bring
- B.Tech/M.Tech in Electrical Engineering, VLSI, or Microelectronics
- 6+ years SRAM circuit design experience
- Proficiency with Cadence Virtuoso or SPICE
- Python or Perl scripting
Skills
SRAM designCircuit optimizationSPICE simulationPhysical verificationPython scriptingLayout supervision
Education
B.Tech/M.Tech in Electrical Engineering, VLSI, or Microelectronics