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Silicon Engineer, Design Verification

Bengaluru, Karnataka, India

About the role

The Silicon team at Google designs and builds high-performance custom silicon and accelerators powering Google machine learning, Google Cloud, and hardware infrastructure. As an ASIC Design Verification Engineer, you will verify next-generation custom silicon accelerators and SoCs, build advanced UVM test environments, and collaborate across design, architecture, and emulation teams to deliver production-quality silicon. You will provide test plans, create constrained-random verification environments, perform power-aware simulations, and drive coverage-driven verification. This role is based in Bengaluru, Karnataka, India.

What you’ll do

  • Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use.
  • Plan the verification of digital design blocks by understanding design specifications and collaborating with design engineers to identify key verification scenarios.
  • Create and improve constrained-random verification environments using SystemVerilog and UVM.
  • Optionally use SystemVerilog Assertions (SVA) and formal tools for formal verification.
  • Perform power-aware simulations and formal verification to validate power management features like clock gating, power gating, and DVFS.
  • Develop and implement power-aware test cases, including stress and corner-case scenarios, for power integrity.
  • Develop and execute coverage-driven verification plans to ensure comprehensive coverage of ASIC designs.
  • Collaborate with design engineers to resolve coverage issues and improve design quality.

What you’ll bring

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 1 year of experience with creating/using verification components and environments in UVM methodology at IP or Subsystem level.
  • Experience developing and maintaining design verification (DV) testbenches, test cases, and test environments.

Nice to have

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience with image processing, computer vision or machine learning IPs.
  • Experience with AMBA (APB/AXI/ACE) or other standard protocols.
  • Familiarity with CPU, GPU or other computer architectures.

Skills

UVM methodologySystemVerilogDesign verification testbenchesConstrained-random verificationSystemVerilog AssertionsFormal verificationPower-aware simulationsCoverage-driven verification

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.