About the role

At NVIDIA, the Circuit Silicon Correlation DFT Engineer role focuses on advancing processor design by bridging pre‑silicon models with real silicon performance. Engineers develop and debug deep sub‑micron circuits, generate ATPG patterns, and perform RTL and gate‑level verification. They analyze silicon failures, correlate them with design parameters, and refine RAM testing methodologies across multiple process nodes. The position requires strong knowledge of DFT concepts—scan, BIST, on‑chip compression, fault models, ATPG, and fault simulation—alongside experience in RTL/gate simulation, VCS, and pattern generation tools like Tessent. Proficiency in scripting (Python, Perl, Tcl, Make) and static timing analysis is essential. Candidates should hold a Bachelor’s in Electrical or Electronics Engineering, have 3+ years of relevant experience, and ideally possess leadership or post‑silicon data gathering experience. The role is hybrid, based in Bengaluru, India, and offers opportunities to shape next‑generation GPU silicon reliability.

What you’ll do

Drive processor design debugging in deep sub‑micron technologies.
Generate ATPG patterns for silicon speed path debugging.
Perform RTL and gate‑level verification of ATPG and non‑ATPG tests.
Correlate diagnosis results to identify real design failures.
Analyze RAM circuit failure mechanisms and improve testing methods.
Develop new DFT methodologies to isolate logic and RAM mis‑correlations.

What you’ll bring

Bachelor's in Electrical/Electronics Engineering (BSEE) required, MS preferred.
3+ years of silicon verification experience.
Deep knowledge of DFT: scan, BIST, on‑chip compression, ATPG, fault simulation.
RTL/gate‑level simulation and testbench development expertise.
Experience with VCS, Tessent, and scripting (Python, Perl, Tcl, Make).

Nice to have

Leadership experience in verification teams.
Post‑silicon data collection and analysis.
Familiarity with static timing analysis (STA).

Skills

DFT design and verificationATPG pattern generationScan chain and BIST implementationFault simulation and analysisRTL/gate‑level simulation (VCS)Pattern generation tools (Tessent)Scripting (Python, Perl, Tcl, Make)Static timing analysis (STA)

Education

Bachelor's