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Hiring companyCadence Design Systems
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Design Engineer II
Hyderabad,India,India Full-time On-site
About the role
Cadence Design Systems' Physical Design team develops and optimizes ASIC implementation flows using Cadence EDA tools. The Design Engineer II creates, automates, and maintains EDA scripts, optimizes PPA for IP cores across advanced process nodes, and manages regression infrastructure. Hyderabad, India, on-site.
What you’ll do
- Develop and automate EDA flows and scripts for physical implementation
- Create TFM to optimize PPA for IPs and soft controllers
- Characterize and optimize flow for performance and power across TSMC, Intel, Samsung, Rapidus
- Manage regression infrastructure tracking RTL/flow quality and PPA
- Implement digital design using Cadence tools such as Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus
- Develop automation scripts using AI tools to reduce turnaround time
- Collaborate with cross-functional teams to ensure design quality
- Provide technical guidance and mentorship
What you’ll bring
- MS/MTech/BE/BTech in Electronics
- 2+ years ASIC design experience
- Physical design experience in ASIC flow
- Knowledge of synthesis, timing, power, formal verification
- Logic synthesis and PPA optimization
- Scripting in Python and Tcl
- Leadership and communication skills
- Team player
Skills
ASIC Physical DesignPPA OptimizationEDA AutomationPython ScriptingTcl ScriptingCadence ToolsLogic SynthesisTeam Leadership
Education
MS/MTech/BE/BTech in Electronics