Senior Engineer II - Design Engineer

About the role

Senior Engineer II – Design Engineer at Microchip Technology leads the design and development of advanced FPGA‑based solutions and SoC components within the FPGA Business Unit. The role requires strong technical leadership, deep RTL design expertise in Verilog/SystemVerilog, and hands‑on experience across the full chip lifecycle—from microarchitecture definition to post‑silicon validation. Responsibilities include defining microarchitecture specifications, driving performance, power, and area optimization, integrating complex IP blocks into FPGA fabric and SoC designs, developing test plans, and debugging pre‑ and post‑silicon issues. The engineer will prototype and emulate designs on FPGA platforms, support hardware bring‑up, and participate in silicon validation and system‑level tuning. Collaboration with architecture, software, and product teams, mentoring junior engineers, and promoting best practices are essential. The position offers the opportunity to work on cutting‑edge FPGA and SoC technologies with global teams.

What you’ll do

• Define microarchitecture specs for FPGA subsystems and SoC components
• Perform RTL design in Verilog/SystemVerilog, optimize performance, power, area
• Integrate IP blocks into FPGA fabric and SoC designs, collaborate on test plans
• Develop RTL for FPGA prototyping, support hardware bring‑up, debug with oscilloscopes
• Participate in silicon validation, characterization, co‑validation, system tuning
• Collaborate with architecture, software, product teams, mentor juniors

What you’ll bring

• 8-12 yrs ASIC/FPGA design, 5+ yrs technical leadership
• Bachelor in Electrical/Electronics/VLSI Engineering
• RTL coding in Verilog/SystemVerilog, SoC architecture, low‑power design
• IP integration, AXI/AMBA bus, DDR, Ethernet, USB, PCIe, MIPI DSI/CSI
• FPGA tools Xilinx Vivado, Intel Quartus, Lattice Diamond; static checks Lint, CDC, synthesis, STA, ECOs

Nice to have

• PCIe Gen4/5, DDR4/5, LPDDR4X, MIPI DSI/CSI, Ethernet MAC, USB, ARM/RISC‑V
• Post‑silicon debug, emulation, hardware prototyping, FPGA acceleration platforms
• Python, TCL/TK, C/C++ automation; Cadence/Mentor simulation; Git, Perforce
• Strong analytical, cross‑site leadership, global communication

Skills

Education

Bachelor