Engineer II, Layout Design

About the role

SiTime Layout Design Team builds precision timing MEMS solutions powering AI datacenters, autonomous vehicles, and IoT. The Layout Design Engineer II leads block-level chip planning and custom analog layout for CMOS/BiCMOS circuits, collaborates with global design teams, and mentors offshore layout engineers. Bangalore, Karnataka, India, on-site work model.

What you’ll do

• Lead and perform custom analog layout design at block and cell levels
• Create area-efficient functional block layouts meeting circuit requirements
• Develop floor plans, power distribution networks, shielding structures
• Verify layouts and ensure DRC/LVS/ERC signoff
• Support chip integration, verification, and tape-out activities
• Train and mentor junior layout engineers and offshore contractors
• Contribute to best practices and workflow improvements across sites
• Collaborate remotely with global design and layout teams

What you’ll bring

• 5+ years layout design for analog and full-custom digital blocks
• Experience with TSMC 180nm, 65nm, 22nm processes
• Proficiency with Cadence Virtuoso layout tools
• Solid knowledge of DRC, LVS, ERC debugging
• Understanding of layout parasitics, matching, crosstalk
• Ability to solve electromigration and power distribution challenges
• Experience with chip-level floorplanning and tape-out
• Ability to lift up to 5 lbs

Benefits

• Quarterly innovation bonus
• Equity grants

Education

BA/BS