Design Engineer II

About the role

Design Engineer II Cadence Design Systems Apply Now on Workday Raw Job Data: This page contains the complete JSON response from the Workday API for this job posting. You can copy the JSON data below for analysis or processing. Complete Job JSON Data Copy JSON { "jobPostingInfo": { "id": "d1bbeffd71a210005e02e574060e0000", "title": "Design Engineer II", "jobDescription": " At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Minimum Qualifications: 2-4 years (with Btech) or 1-2 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation Deep Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO etc Strong hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etc Preferred Qualifications: Experience managing small teams (at least 2 members and above) Experience leading the complete post silicon validation efforts for at least one full project 1-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug. Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C\+\+;, TCL Experience conducting hiring interviews and mentoring new hires BE/BTech/ME/MTech or equivalent We’re doing work that matters. Help us solve what others can’t. ", "location": "BANGALORE", "postedOn": "Posted 30+ Days Ago", "startDate": "2024-07-17", "timeType": "Full time", "jobReqId": "R45986", "jobPostingId": "Lead-Design-Engineer_R45986", "jobPostingSiteId": "External_Careers", "country": { "descriptor": "India", "id": "c4f78be1a8f14da0ab49ce1162348a5e" }, "canApply": true, "posted": true, "includeResumeParsing": true, "jobRequisitionLocation": { "descriptor": "BANGALORE 05", "country": { "descriptor": "India", "id": "c4f78be1a8f14da0ab49ce1162348a5e", "alpha2Code": "IN" } }, "externalUrl": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Design-Engineer_R45986" }, "hiringOrganization": { "name": "", "url": "" }, "similarJobs": [ { "title": "Principal Design Engineer", "externalPath": "/job/BANGALORE/Principal-Design-Engineer_R40668", "timeType": "Full time", "locationsText": "BANGALORE", "postedOn": "Posted 30+ Days Ago", "startDate": "2022-10-03" }, { "title": "Principal Design Engineer", "externalPath": "/job/BANGALORE/Principal-Design-Engineer_R46243", "timeType": "Full time", "locationsText": "2 Locations", "postedOn": "Posted 30+ Days Ago", "startDate": "2024-07-24" }, { "title": "Product Engineer II", "externalPath": "/job/BANGALORE/Product-Engineer-II_R47885-2", "timeType": "Full time", "locationsText": "BANGALORE", "postedOn": "Posted 4 Days Ago", "startDate": "2025-07-23" }, { "title": "Software Engineer II", "externalPath": "/job/BANGALORE/Lead-Software-Engineer_R47454-3", "timeType": "Full time", "locationsText": "BANGALORE", "postedOn": "Posted 30+ Days Ago", "startDate": "2025-05-01" }, { "title": "Lead design Engineer", "externalPath": "/job/BANGALORE/Lead-design-Engineer_R46636", "timeType": "Full time", "locationsText": "BANGALORE", "postedOn": "Posted 30+ Days Ago", "startDate": "2025-06-04", "jobPostingEndDateAsText": "End Date: August 12, 2025" } ], "userAuthenticated": false }

What you’ll do

• Validate post-silicon physical layer for high-speed SERDES protocols
• Operate oscilloscopes, network analyzers, BERT for signal integrity
• Design FPGA, PCB schematics, layouts, and prototypes
• Lead small teams and full validation projects
• Conduct hiring interviews and mentor new hires

What you’ll bring

• 2-4 yrs (BTech) or 1-2 yrs (MTech) Post-Silicon Physical Layer Validation
• Deep validation on at least one high-speed SERDES: PCIe, USB, DP, Ethernet, SRIO, JESD204, DDRIO
• Hands-on lab skills: Oscilloscope, Network Analyzer, BERT

Nice to have

• Lead small teams (≥2) and full post-silicon validation projects
• 1‑2 yrs FPGA, PCB schematic/layout design & prototyping
• Pre-silicon IP/SoC Physical Layer Validation for board bring-up & debug
• Familiar with Verilog RTL, FPGA coding, LabVIEW, Python, C/C++, TCL
• Conduct hiring interviews, mentor new hires
• BE/BTech/ME/MTech or equivalent

Skills

Education

Bachelor's/Master's