Principal Design Verification Engineer

About the role

Marvell’s Design Verification Team seeks a Principal Design Verification Engineer to architect functional verification environments for high‑speed SoCs. The role involves writing detailed test plans, building directed and random verification environments, debugging failures, and verifying boot code. Candidates will develop and maintain tools that streamline multi‑core SoC design, transform engineering requirements into scalable software, and perform unit and regression testing. The position requires deep expertise in SystemVerilog, UVM, Python/Perl scripting, EDA tools, and object‑oriented design, with strong Linux, C++, and ARM assembly skills. A BS/MS in Computer Engineering, Electrical Engineering, or Computer Science with 10+ years of verification and firmware/software experience (or PhD with 5+ years) is essential. Diligence, initiative, and the ability to thrive in a fast‑paced environment are critical.

What you’ll do

• Design verification architecture for functional environment
• Write verification test plans with random techniques and coverage analysis
• Develop tests, tune environment, debug failures, resolve issues
• Verify boot code, develop and maintain tools for multi‑core SoCs
• Transform engineering requirements into scalable software tools
• Unit and regression test software tools

What you’ll bring

BS/MS in Computer Engineering, Electrical Engineering, or Computer Science with 10+ years verification and firmware/software dev experience (or PhD with 5+ years)

Nice to have

• SystemVerilog, UVM, detailed test plan, directed/random verification environment
• Python or Perl scripting, EDA verification tools
• Object-Oriented Design, Linux OS, C++ and ARM assembly
• Networking protocols knowledge

Skills

Education

BS/MS