Principal Engineer, Design Verification

About the role

Principal Verification Engineer leading end‑to‑end functional verification of complex ASIC/SoC designs. Owns UVM/SystemVerilog strategy, interprets Ethernet specifications, architects scalable VIPs, drives coverage, ensures first‑pass silicon success, leads bug triage, mentors teams, and collaborates across architecture, RTL, firmware, and software to deliver high‑quality silicon.

What you’ll do

• Own verification strategy (UVM/SystemVerilog) at IP, subsystem, SoC levels.
• Interpret Ethernet specs, create verification plans, assertions, test scenarios.
• Architect scalable verification environments, reusable VIPs, checkers.
• Drive coverage-driven verification: functional, code, assertion coverage.
• Lead verification planning, testbench architecture, test plan sign‑off.
• Review complex test scenarios, corner cases.
• Ensure first‑pass silicon success via functional, protocol compliance.
• Lead bug triage, root‑cause analysis, closure across IP, subsystem, SoC.
• Track verification metrics, KPIs, sign‑off criteria.
• Validate performance, stress, corner scenarios (congestion, backpressure, error injection).
• Support emulation, FPGA prototyping, post‑silicon validation for Ethernet bring‑up.
• Collaborate with architecture, RTL, DFT, physical design, firmware, software teams.
• Provide early verification input during architecture definition, standards compliance.
• Collaborate with software on driver, firmware, traffic validation.
• Mentor verification engineers across experience levels.
• Enforce verification best practices, coding standards.
• Drive continuous improvements in verification flows, reuse, productivity.

What you’ll bring

• Bachelor's or Master's in Electrical/Electronics Engineering
• 10+ years ASIC/SoC design verification experience
• Strong hands‑on SystemVerilog, UVM, SVA expertise
• Deep Ethernet architecture and protocol knowledge (MAC, PCS, PHY)

Skills

Education

Bachelor's or Master's in Electrical/Electronics Engineering