Principal Verification Engineer

About the role

Digital Verification team at EnSilica builds verification solutions for semiconductor designs. The Principal Verification Engineer leads verification strategy, designs test environments, and mentors teams on UVM/SystemVerilog across customer and internal projects. Based in Bangalore, India office, on-site work model.

What you’ll do

• Lead verification efforts for customer and internal projects
• Develop comprehensive verification strategies and test environments
• Implement verification infrastructures using UVM/SystemVerilog
• Apply advanced techniques like constrained random, coverage, assertions, formal methods
• Collaborate with customers to build relationships and drive repeat business
• Mentor and guide verification team members
• Participate in verification community to introduce new techniques
• Monitor verification metrics to assess progress

What you’ll bring

• 10+ years verification experience
• Expertise in SystemVerilog and UVM
• Experience with constrained random and coverage-driven verification
• Proficiency in Verilog/VHDL RTL
• Familiarity with Mentor Questa and Cadence Incisive
• Knowledge of ISO26262 functional safety
• Strong communication and presentation skills
• Leadership in verification strategy

Nice to have

• 10+ years verification experience
• Expertise in SystemVerilog and UVM
• Experience with constrained random and coverage-driven verification
• Proficiency in Verilog/VHDL RTL
• Familiarity with Mentor Questa and Cadence Incisive
• Knowledge of ISO26262 functional safety
• Strong communication and presentation skills
• Leadership in verification strategy

Skills