Principal Engineer, Verification

About the role

Verification Team at Microchip Technology designs and validates block-level digital designs. The Principal Engineer creates verification test plans, develops SystemVerilog/UVM test environments, runs regressions and analyzes coverage to ensure design quality. Based in Chennai, India, on-site work model.

What you’ll do

• Develop verification test plans from design specifications
• Create SystemVerilog/UVM test environments and test benches
• Integrate with RTL and perform simulation bring-up
• Generate and analyze functional and code coverage
• Create and launch regression test cases
• Collaborate with design team to resolve issues
• Drive self‑motivated solutions for new requirements

What you’ll bring

• Bachelor's or Master's in Electrical/Electronic Engineering
• 10+ years of verification experience
• Domain expertise in AHB, AXI, PCIe, USB, Ethernet
• Proficient in Verilog and SystemVerilog
• Experience with OVM/UVM methodologies
• Familiar with Questasim, VCS, NCSim, NCVerilog tools
• Developed block‑level and SOC‑level test benches
• Strong analytical and communication skills

Skills