Verified today
Principal Verification Engineer
About the role
Altera seeks a Principal Verification Engineer to design, develop, and validate FPGA-based acceleration solutions for embedded, data‑center, and communications clients. The role requires deep expertise in SystemVerilog, UVM, and HDL verification, with a focus on coverage‑driven and assertion‑based methodologies. Candidates will collaborate with architects and design engineers to create comprehensive verification strategies, develop reusable testbenches, and implement directed and random test cases. They will also leverage formal verification, SVA, and automation scripts in Python or Perl to enhance bug detection and streamline regression flows. Strong analytical, debugging, and communication skills are essential, as is experience with industry protocols such as AMBA, PCIe, and Ethernet. The position offers a hybrid work model, with remote work from New Delhi and onsite collaboration in Bengaluru.
What you’ll do
- Collaborate with architects to define verification strategies
- Develop reusable, constrained‑random verification environments
- Create directed and random test cases and sequences
- Build verification components: drivers, monitors, scoreboards
- Apply SystemVerilog Assertions and formal methods
- Execute regressions, debug failures, analyze root causes
- Track coverage metrics and drive closure
- Automate scripts to improve verification efficiency
- Participate in technical reviews of specs and test plans
What you’ll bring
- Bachelor's or Master's in Electrical/Computer Engineering or related field
- 10+ years ASIC/FPGA verification experience
- Proficient in Verilog/VHDL and SystemVerilog
- Hands‑on UVM testbench development
- Coverage‑driven and assertion‑based verification expertise
- Familiarity with AMBA, PCIe, Ethernet protocols
- Experience with simulation/debug tools
- Strong scripting in Python, Perl, or TCL
- Excellent analytical and debugging skills
- Strong communication and teamwork
Skills
Education
Bachelor's or Master's