Verified 4 days ago
Principal Engineer Verification
About the role
Verification team at Infineon Technologies, a global leader in semiconductor solutions, ensures the reliability of integrated circuits through rigorous simulation, verification and validation. The Principal Engineer leads development of SystemVerilog/UVM testbenches, drives verification metrics, and collaborates with cross‑functional teams on post‑silicon bring‑up and compliance testing. Hyderabad, on-site, full‑time role.
What you’ll do
- Develop and supervise SystemVerilog/UVM testbenches and components
- Create test plans, sequences, and coverage metrics
- Provide regression setup and debug RTL and gate‑level netlists
- Collaborate with architects, designers, and project leads
- Present verification status in design reviews and customer meetings
What you’ll bring
- Bachelor's in Electrical Engineering or equivalent
- 12+ years verification experience
- Expertise with UVM and SystemVerilog
- Strong ASIC verification methodology knowledge
- Experience with Jenkins, Git, Jira