About the role

Principal Design Verification Engineer at onsemi leading verification strategy for embedded MCU, DSP, and cryptographic accelerators. Drives UVM/SV environments, coordinates cross-functional teams, mentors junior engineers, and enhances verification methodology across global projects.

What you’ll do

Define verification strategy and plans for blocks and systems
Lead verification activities and achieve project closure
Develop SystemVerilog/UVM environments for blocks and SoCs
Debug functional RTL errors
Improve verification methodology
Mentor junior engineers

What you’ll bring

BS/MS Electrical Engineering or related field
13+ years digital verification experience
Expertise in UVM, constrained random, assertion-based verification
Strong verification planning, coverage, regression management

Nice to have

CPU/MCU subsystem verification
SystemRDL or IP-XACT experience
Python automation programming
C/C++ embedded software
Signal processing component verification
3rd party verification IP deployment

Skills

SystemVerilogUVMPythonC/C++Verification PlanningCoverage AnalysisRegression ManagementFormal VerificationAssertion-Based VerificationConstrained Random VerificationSignal Processing VerificationIP-XACTSystemRDL

Benefits

Competitive benefit package
Volunteer & charitable programs

Education

Bachelor