Principal Design Verification Engineer

About the role

AISiE silicon team designs cutting-edge custom IP and SoCs. The Principal Design Verification Engineer leads verification of complex SOC, subsystem, and IP flows, plans strategies, develops environments, runs simulations, applies random‑stimulus and coverage techniques, and mentors team members. Bengaluru and Noida, India, on-site.

What you’ll do

• Lead verification of complex SOC/IP flows
• Plan verification strategies and test plans
• Develop verification environments and run simulations
• Apply random‑stimulus and coverage‑based techniques
• Innovate verification efficiency methodologies or tools
• Coach and mentor team members

What you’ll bring

• 15+ years design verification experience
• Verification of CPU/SoC IP using UVM or C++
• Debugging RTL (Verilog) designs
• Python or Perl scripting
• Knowledge of DDR/HBM, PCIe, Ethernet protocols

Skills