Senior Design Verification Engineer

About the role

Holoscan FPGA team at NVIDIA builds next‑generation FPGA platforms that power real‑time AI, healthcare, robotics, and automotive edge solutions. The Senior Design Verification Engineer leads verification strategy, creates scalable constrained‑random UVM environments, and drives stimulus and coverage to meet product milestones while collaborating with design and architecture groups. Bengaluru, hybrid work model, relocation assistance available.

What you’ll do

• Define, plan, implement and execute verification strategy for Holoscan Edge FPGA designs
• Create scalable constrained‑random verification environments using SystemVerilog and UVM
• Drive stimulus generation and comprehensive coverage to meet product milestones
• Collaborate with design and architecture teams to verify architectural features
• Analyze and improve verification strategies, incorporating AI‑accelerated workflows

What you’ll bring

• 3+ years ASIC verification experience
• Proficiency in SystemVerilog and UVM
• Knowledge of SVA or functional coverage
• Python or Perl scripting skills
• Strong understanding of verification methodologies and tools
• Excellent communication and teamwork abilities
• Problem‑solving skills and attention to detail

Skills

Education

Bachelor's or Master's in Electrical Engineering, Computer Engineering or related field