Verified today
Senior Design Verification Engineer
About the role
onsemi Design Verification team builds advanced mixed-signal IP for automotive, industrial and medical applications. The Senior Design Verification Engineer defines verification strategies, leads verification activities, and creates SystemVerilog/UVM environments while debugging RTL errors. Bangalore, India, on-site role with hybrid collaboration across project teams.
What you’ll do
- Define verification strategy and detailed plans for blocks and systems
- Coordinate and lead verification activities within project teams
- Develop SystemVerilog/UVM environments for blocks and top‑level SoCs
- Debug functional errors in RTL
- Participate in verification methodology improvement activities
What you’ll bring
- BS/MS in Electrical Engineering or related field
- 3+ years digital verification experience
- Solid understanding of verification planning, requirements tracking and functional coverage
- Expertise in UVM, constrained random and assertion based verification
- Excellent English written and verbal communication
- Project/task leadership experience
- Verification of signal processing components
- Programming skills in Python and Tcl
Skills
Education
Bachelors