Verified today
Senior Design Verification Engineer
About the role
Design Verification Team at onsemi develops advanced mixed-signal IP for automotive, industrial and medical products. The Senior Design Verification Engineer defines verification strategies, leads project verification activities, builds SystemVerilog/UVM environments, and debugs RTL functional errors while improving methodology. Bangalore, India, on-site, Full-time.
What you’ll do
- Define verification strategy and detailed plans
- Coordinate and lead verification activities
- Develop SystemVerilog/UVM environments for blocks and SoCs
- Debug functional errors in RTL
- Participate in verification methodology improvement
What you’ll bring
- BS/MS Electrical Engineering or related field
- 3+ years digital verification experience
- Understanding of verification planning and coverage
- Experience with UVM and constrained random verification
- Excellent English communication
- Project/task leadership experience
- Verification of signal processing components
- Python, Tcl, embedded software skills