Senior Design Engineer, Design Verification

About the role

Hardware Engineering team at Quadric builds cutting‑edge edge AI processors. The Senior Design Verification Engineer will architect and implement a scratch‑built UVM verification environment for Quadric's GPNPU‑based SoCs, creating test plans, drivers, and co‑simulation pipelines. Works closely with architects, hardware designers, and software teams in Pune, on‑site, to ensure comprehensive verification coverage and meet target metrics.

What you’ll do

• Architect and build SoC‑level UVM testbenches
• Develop comprehensive verification test plans
• Create directed and random drivers, assembly/C++ programs
• Execute test suites using VCS, co‑simulation, and Python scripts
• Track and report functional and code coverage metrics
• Collaborate with hardware and software teams to resolve issues
• Establish co‑simulation pipelines for HW/SW validation

What you’ll bring

• 5+ years design verification on complex SoC/ASIC
• Deep expertise in UVM methodology
• Proficiency in SystemVerilog or Verilog
• Assembly programming and Python scripting
• Experience verifying 3rd‑party IP (NoC, PCIe/UCIe, DDR)
• Strong computer architecture background
• Hands‑on with VCS and Verilog/C co‑simulation

Skills

Benefits

• Medical, dental, and vision insurance
• Equity participation
• Paid parental leave
• PF retirement plan
• Flexible PTO