Senior Design Verification Engineer

About the role

Google's custom silicon team develops cutting‑edge hardware for its consumer products. The Senior Design Verification Engineer creates and enhances constrained‑random and formal verification environments, defines test and coverage plans, and leads functional verification of memory subsystem IPs. Bengaluru, on-site, hybrid collaboration with design, architecture, and validation teams.

What you’ll do

• Develop detailed test and coverage plans for complex IPs
• Create constrained‑random verification environments using SystemVerilog/UVM
• Perform formal verification using SVA and industry‑leading tools
• Collaborate with design, architecture, and silicon validation teams
• Serve as primary point of contact for functional verification of assigned blocks

What you’ll bring

• Bachelor's degree in Electrical Engineering or Computer Science or equivalent practical experience
• 8 years of design verification experience

Nice to have

• Proficiency with SystemVerilog and UVM
• Experience with verification of ASICs and memory subsystem architectures
• Knowledge of SystemVerilog Assertions and formal verification tools

Education

Bachelor's