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ASIC Engineer, Implementation, Low-Power Design
Bangalore,,India Full-time
About the role
Meta Silicon Engineering team builds custom silicon powering Meta's AI and data center workloads. The ASIC Engineer, Implementation focuses on low-power design, developing power modeling flows in Python/C++, driving implementation from RTL to tapeout, and optimizing power across synthesis, place-and-route, and signoff. Bangalore, India, on-site.
What you’ll do
- Define power specifications at system and module level
- Develop power modeling infrastructure in Python/C++
- Build power estimation flows at C-model, RTL, gate, and layout levels
- Apply ASIC design knowledge to evaluate leakage and dynamic power
- Collaborate with RTL designers to resolve timing, area, and power issues
- Participate in design reviews influencing architectural decisions
- Characterize power on silicon and debug power issues
- Partner with EDA and silicon vendors for low-power requirements
What you’ll bring
- 2+ years experience with C++ or Python
- Experience with Synopsys Design Compiler, Cadence Genus, Innovus or ICC-2
- Scripting in Tcl, Python or Perl for flow automation
- RTL design using SystemVerilog
- Familiarity with low-power techniques like clock gating and power gating
- Background in data center or AI accelerator ASIC development
- Experience with post-silicon bringup and debugging
- Masters degree in relevant field
Skills
Power ModelingLow-Power DesignASIC ImplementationPythonC++EDA ToolsRTL DesignSystemVerilog
Education
- Bachelor's
- Master's