NPU/AI Processor Synthesis - Principal Engineer/Manager

About the role

Hardware Engineering team at Qualcomm drives cutting‑edge SoC development. The NPU Synthesis Lead owns RTL‑to‑gate synthesis, timing closure, and PPA optimization for AI processor IP, collaborating with architecture, RTL, and physical design groups. Leads a team of engineers, mentors junior staff, and innovates synthesis flows. Bangalore office, on‑site work model, relocation assistance available.

What you’ll do

• Lead RTL‑to‑gate synthesis for NPU IP using Design Compiler and Genus
• Develop and maintain hierarchical synthesis scripts and flows
• Drive pre‑layout and post‑layout timing closure across voltage and process corners
• Apply low‑power techniques with UPF/CPF and optimize area and performance
• Validate SDC constraints and perform LEC, CLP, and lint checks
• Collaborate with RTL, DFT, and physical design teams for seamless handoff
• Mentor junior engineers and promote best practices in synthesis and timing

What you’ll bring

• Bachelor's degree in Electrical/Electronics Engineering or related field
• 6+ years ASIC hardware engineering experience
• 5+ years synthesis and timing closure expertise
• 3+ years NPU or AI processor design experience
• Proficiency with Synopsys Design Compiler, Cadence Genus, and PrimeTime
• Advanced scripting skills in Tcl, Perl, Python
• Experience with low‑power UPF/CPF flows
• Familiarity with Spyglass, CDC, and power analysis tools

Skills