About the role

Principal Digital Design Engineer at onsemi focuses on leading digital design architecture, RTL implementation, and low‑power design for power management ICs, collaborating across global teams and driving tool flows for IP quality control.

What you’ll do

Lead digital design architecture for power management chips
Drive RTL implementation and tool flows for IP quality control
Collaborate with design architects, verification, project management, analog teams worldwide
Support bring‑up of features on SOC, emulation, FPGA platforms
Validate designs post‑silicon
Recommend new systems, tools, processes to improve design reuse

What you’ll bring

BS in Electrical Engineering or related +10 years experience
MS +8 years experience in Digital Design, Architecture, ASIC/Mixed signal chip development
Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis, P&R, UPF, SystemVerilog
Proficiency in Verilog, TCL, Perl/Python/XML programming
Experience developing ASIC/Mixed signal ICs for power converters (DC-DC, PMIC, LED drivers)
Knowledge of topologies for constant-on-time, peak, valley control, hysteretic, multi-phase, smart power stages
Understanding of digital architecture trade-offs for power, performance, area
Strong written and verbal cross‑functional communication skills

Skills

Digital RTL designLow power designSynthesis and timing analysisBehavioral codingDigital architectureASIC synthesisP&R, UPF, SystemVerilogVerilog, TCL, Perl/Python/XMLASIC/Mixed signal IC developmentPower converter topologiesDigital architecture trade‑offsCross‑functional communication

Benefits

Company benefits available at onsemi.com/careers/career-benefits

Education

Bachelor's