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Hiring companyNXP Semiconductors

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Principal DFT Engineer

Pune, India Full-time On-site

About the role

Principal HW DFT Engineer at NXP Semiconductors to architect, implement, and validate in-vehicle networking devices for automotive grade products. Responsibilities include advanced DFT strategy design (Scan, JTAG, MBIST, LBIST), integration of digital subsystems, scan insertion, ATPG pattern generation, post-silicon validation, debugging, and collaboration with physical design and test engineering teams to ensure timing closure and operational test patterns. Requires 10+ years industry experience in SoC DFT implementation, verification, static timing closure, test coverage analysis, silicon bring-up on ATE, proficiency with Mentor Graphics/Siemens Tessent, Cadence, Synopsys tools, HDL (Verilog/SystemVerilog), STA, SDC, gate-level simulation, post-silicon debug, scripting (Tcl/Python/Perl).

What you’ll do

  • Architect and implement advanced DFT strategies for automotive in-vehicle networking devices.
  • Lead integration of digital subsystems, perform scan insertion, generate ATPG patterns.
  • Drive post-silicon validation and debug to root cause failures and improve manufacturing test efficiency.
  • Coordinate with physical design and test engineering teams to ensure timing closure and operational test patterns.

What you’ll bring

  • Education: B.S./M.S. Electrical/Computer Engineering (or similar degrees)
  • Experience: 10+ years in SoC DFT implementation, verification, static timing closure, test coverage analysis, silicon bring-up on ATE
  • Tool Expertise: Proficiency with Mentor Graphics/Siemens Tessent, Cadence, or Synopsys EDA tools
  • Technical Skills: DFT – Scan insertion, ATPG, BIST (MBIST, LBIST), Boundary Scan & JTAG, Test Compression for SoC designs
  • Hardware Design: HDL (Verilog/SystemVerilog) for RTL modification, test wrappers, STA, DFT-specific SDC constraints
  • Verification & Debug: Gate-level simulation, post-silicon debug using ATE data to improve yield
  • Software & Tool Proficiency: Mastery of Synopsys TestMAX/DFT Compiler, Mentor Tessent, Cadence Modus; scripting in Tcl, Python, Perl

Skills

DFT strategy design (Scan, JTAG, MBIST, LBIST)ATPG pattern generationBIST integrationBoundary Scan & JTAGTest CompressionHDL (Verilog/SystemVerilog)Static Timing Analysis (STA)SDC constraint creationGate-level simulationPost-silicon debugEDA tools: Synopsys, Mentor, CadenceScripting: Tcl, Python, Perl

Education

Bachelor

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