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Hiring companyCadence Design Systems
Verified today
Principal DFT Design Engineer
Bangalore, India Full-time On-site
About the role
Principal DFT Design Engineer at Cadence leads DFT design, mentors juniors, drives innovation, works cross‑functional across geographies. Requires 7+ years experience, BE/B.Tech/M.E/M.Tech, strong DFT concepts, EDA tools, logic simulators, ATPG (Cadence Modus), RTL lint (Jasper), scan insertion, coverage analysis, debugging, scripting (Perl/Tcl/Python). Post‑silicon validation, ATE debug, RTL2GDS flow, synthesis, STA, IR drop, logic design, RTL implementation, verification, logic synthesis, equivalent checking, static timing analysis. Drives new DFT methodology to improve quality, reliability, in‑system test/debug.
What you’ll do
- Lead DFT design and mentor juniors
- Drive innovation and automation
- Align cross‑functional teams on deliverables
- Develop new DFT methodologies
- Enhance quality, reliability, test/debug
What you’ll bring
- 7+ years relevant experience in DFT design
- BE/B.Tech or M.E/M.Tech in Electrical Engineering
- Strong DFT concepts and EDA tool proficiency
- Scan insertion, coverage analysis, debugging skills
- Scripting in Perl/Tcl/Python
- Post‑silicon validation, ATE debug support
- RTL2GDS flow, synthesis, STA, IR drop
Skills
DFT DesignEDA ToolsCadence ModusJasper RTL LintScan InsertionCoverage AnalysisDebuggingPerlTclPythonPost‑Silicon ValidationATE DebugRTL2GDSSynthesisSTAIR DropLogic DesignRTL ImplementationVerificationLogic SynthesisEquivalent CheckingStatic Timing Analysis
Education
Bachelor