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Principal DFT Engineer
About the role
Cadence Design Systems' DFT team builds test solutions for SoC/ASIC designs. The Principal DFT Engineer leads DFT insertion flows, ATPG, MBIST, and collaborates with architecture and design teams to ensure test coverage. Bangalore, on-site.
What you’ll bring
- 7-12 years SoC/ASIC digital design with DFT focus
- Intimate knowledge of DFT insertion flows
- Experience with scan chain insertion and compression scan
- Knowledge of MBIST and ATPG
- Familiarity with JTAG 1149.1/6, IEEE1500, IEEE1687
- Experience with Cadence tools
- Ability to work independently and cross‑functionally
- Strong problem‑solving skills