Principal Digital Engineer (DFT Design)

About the role

Join Renesas' Power Management IC Team within the Automotive Business Unit to build world-class PMIC products for tomorrow's automobiles. You will design complex chips, focusing on digital DFT implementation including scan insertion, ATPG, and logicbist to meet ASIL-B/D requirements. This role is based in Bengaluru, Karnataka, India, with a mandatory hybrid work model requiring on-site presence three days per week.

What you’ll do

• Insert DFT/Scan on digital logic and improve scan coverage by modifying RTL
• Perform ATPG and validate test patterns on pre- and post-layout gate level netlists
• Insert Logicbist using industry standard tools during synthesis or RTL stages
• Reduce ATE tester time by optimizing scan patterns while maintaining required coverage
• Participate in digital design flow including micro-architecture, RTL coding, and synthesis
• Deliver test patterns to Test Engineering and validate them on silicon
• Debug scan pattern fails on ATE and fix scan patterns
• Write detailed design documents and own the design to meet specifications

What you’ll bring

• Masters degree plus 12+ years or Bachelors plus 15+ years experience in digital design and DFT
• BSEE required (MSEE preferred)
• Hands-on experience with Scan insertion, ATPG, Logicbist, and RTL coding
• Experience with at least 8 tapeouts involving DFT/Scan
• Proficiency in industry standard tools like Synopsys, Cadence, Mentor, or Siemens
• Strong fundamentals in digital design, synthesis, and timing constraints

Nice to have

• Mixed signal experience
• Exposure to automotive test requirements and ASIL standards

Skills

Benefits

Competitive benefits package alongside salary

Education

BSEE required (MSEE preferred)