Verified today
Staff Engineer, Design Verification Engineering
About the role
Design Verification Engineering team at Analog Devices develops verification strategies for complex analog and mixed-signal designs. The Staff Engineer architects sophisticated UVM verification environments, mentors junior engineers, and leads cross‑functional verification efforts to ensure product quality. Bangalore, on-site, hybrid schedule with occasional travel (10%).
What you’ll do
- Architect verification strategy for complex designs
- Design and implement UVM‑based verification environments
- Mentor and guide junior engineers
- Coordinate cross‑functional verification requirements
- Lead debugging of RTL and gate‑level simulations
- Drive functional and code coverage closure
- Lead post‑silicon validation activities
- Represent customers in technical discussions
What you’ll bring
- SystemVerilog
- UVM
- Mixed‑Signal Verification
- Debugging
- EDA Tools (Cadence/Synopsys)
- Python/Perl/TCL/Shell scripting
- Verification Architecture
- Technical Leadership
Skills
Education
MS/PhD in Electrical Engineering, Computer Engineering, or related field