Sr Staff Engineer, Design Verification

About the role

Renesas seeks a Sr Staff Engineer to verify digital multi-core SoCs, ensuring product quality for automotive and IoT markets. The role involves coding simulation infrastructure in SystemVerilog/UVM, developing test benches, and managing verification plans across the product development lifecycle. This position is based in Bengaluru, Karnataka, India.

What you’ll do

• Code simulation infrastructure using SystemVerilog (UVM) & C/Assembly
• Set up UVM verification environments and develop self-tested test benches
• Generate verification plans from specifications using vManager
• Determine coverage and design completeness requirements
• Create assertions, cover-groups, checkers, and monitors
• Run regression reports and analyze results
• Participate in all stages of product development including silicon debug
• Develop advanced mixed-signal simulation techniques to enhance efficiency

What you’ll bring

• BSEE or equivalent with 10+ years professional industry experience
• Extensive experience in Digital multi core SoC verification
• Proficiency in SystemVerilog (UVM) and C/Assembly
• Experience with Mixed-signal verification methodologies
• Ability to work independently with limited supervision

Nice to have

• MSEE degree preferred
• Experience with UVM testbench creation and implementation
• Proficiency in scripting languages such as Shell, Perl, or Python
• Knowledge of Cadence SKILL language

Skills