Senior Principal Digital Design Engineer

About the role

Senior Principal Digital Design Engineer leads the design of power management ICs, overseeing RTL implementation, low‑power architecture, and system‑level validation across LED, SiC, and smart‑switch products. The role requires deep expertise in digital RTL, synthesis, timing analysis, and verification, as well as collaboration with analog, verification, and project teams worldwide. Responsibilities include defining micro‑architecture, driving feature refinement, coordinating pre‑silicon bring‑up on FPGA and emulation platforms, and supporting post‑silicon validation and customer issues. The position demands strong communication skills, project management acumen, and a proven track record of delivering complex ASIC/Mixed‑signal designs to market.

What you’ll do

• Lead RTL implementation of power driver digital controls for LED/SiC/smart‑FET/Efuse applications
• Define and refine micro‑architecture to RTL with feature requirements
• Coordinate pre‑silicon bring‑up on SOC, emulation, and FPGA platforms
• Own design verification, implementation, and execution of Power Management ICs
• Support post‑silicon validation, customer issues, and production support

What you’ll bring

• BS Electrical Engineering + 14 years experience
• MS Electrical Engineering + 12 years experience
• Solid understanding of RTL design, CDC, synthesis, timing analysis, UPF, SystemVerilog

Skills

Education

Bachelor's