Verified 4 days ago
Senior IP Design Engineer
About the role
Hardware Engineering team at Google develops custom silicon solutions for data center accelerators. The Senior IP Design Engineer leads RTL and micro-architecture design of high‑performance fabrics and Network‑on‑Chip subsystems, runs power‑performance‑area analysis, and collaborates with verification, physical design, and architecture teams to deliver tape‑out ready IP blocks. Bengaluru, on-site, hybrid collaboration with cross‑functional teams.
What you’ll do
- Own RTL and micro‑architecture development for NoC fabrics
- Perform PPA analysis and design trade‑offs
- Write production‑quality SystemVerilog code for complex logic
- Drive front‑end implementation and debug Lint, CDC, RDC, LEC
- Collaborate with physical design for floorplanning and timing closure
- Debug silicon issues and architectural bugs
What you’ll bring
- 8 years RTL design experience
- Proficiency in Verilog/SystemVerilog
- Experience with high‑speed NoC design
- Bachelor's in EE/Computer Engineering or equivalent
Skills
Education
Bachelor's