Senior SoC Design Verification Engineer

About the role

Senior SoC Design Verification Engineer with 8+ years in ASIC and SoC verification. Expert in SystemVerilog, UVM, and formal methods, building testbenches and test cases for full‑chip and system‑level validation. Skilled in Linux/Unix scripting with Perl and Python, and experienced with ARM‑based SoC verification across PCIe, Ethernet, USB, and TSN protocols. Proficient in debugging design using JTAG, high‑speed USB, and PCIe debug interfaces. Adept at defining verification strategies, test plans, and coordinating cross‑functional teams with Design, SW, and Architecture to achieve full coverage. Flexible and communicative, thriving in dynamic environments and distributed teams. Adds value with emulation experience.

What you’ll do

• Pre‑silicon system verification (SoC, FPGA, Full Chip)
• Create UVM testcases/testbench
• Define verification strategies, test plans for full‑chip/system
• Coordinate cross‑functional Design, SW, Architecture teams
• Emulation experience (add on)

What you’ll bring

• 8+ yrs ASIC design/verification experience
• Proficient in SystemVerilog, UVM, formal methods
• Linux/Unix scripting, Perl/Python skills
• ARM SoC verification, PCIe/Ethernet/USB/TSN protocols
• Debug design (JTAG, high‑speed USB, PCIe debug)
• Strong communication, cross‑geography teamwork
• Adaptable in dynamic environments

Skills