Principal Engineer, ASIC Analog Design

About the role

Micron Technology seeks a Principal Engineer in ASIC Analog Design to lead high‑speed PHY analog sub‑block development on 12nm and below nodes. The role requires ownership of PLL, DLL, CDR, and high‑speed receiver/transmitter front‑ends, driving specification, implementation, and layout with DFM compliance. Responsibilities include design reviews, IP EDA view creation, silicon bring‑up, characterization, and correlation with models. The engineer will mentor junior staff and collaborate across multiple sites. Candidates must have deep analog/mixed‑signal CMOS expertise, FinFET 10nm+, Verilog‑A/Python modeling, and proficiency with Cadence, Spectre, EM/IR, MATLAB, and Calibre. Strong knowledge of high‑speed interfaces (DDR, LPDDR, GDDR, SerDes) and ESD is essential.

What you’ll do

• Design high‑speed PHY analog sub‑blocks, 12nm+ nodes
• Specify and implement analog sub‑blocks, drive layout & DFM
• Lead design reviews, explain choices to internal & customer teams
• Create IP EDA views: Verilog‑A, timing, abstract models
• Conduct silicon bring‑up, characterization, model correlation
• Mentor junior engineers, foster skill growth

What you’ll bring

• Analog/mixed-signal CMOS circuit design 2–28 nm, DDR/LPDDR/GDDR, SerDes
• Own sub-blocks: PLL, DLL, CDR, high-speed receiver, transmitter front-end
• Deep knowledge of high-speed links, TX/RX equalization (FFE/CTLE/DFE)
• FinFET 10nm+ design, AMS fundamentals, device physics, Monte‑Carlo analysis
• Block‑level spec from link budget, system modeling with Verilog‑A/Python
• Layout of complex analog blocks, IP floorplan, DFM compliance
• Tools: Cadence ADE, Spectre, AMS verification, EM/IR, MATLAB, Calibre
• Mixed‑mode simulation, signal integrity, ESD, high‑speed I/O (DDR, LVDS, HSTL, CML)
• Lab testing, validation data analysis, packaging/board collaboration
• Experience with SerDes/parallel interfaces, CDR/clocking architectures

Skills

Education

Bachelor's/Master's