Senior Principal ASIC / RTL Design Engineer

About the role

onsemi seeks a Senior Principal ASIC/RTL Design Engineer to lead digital design and architecture for power management products in Bengaluru. The role involves trade‑off analysis, platform development, RTL design, low‑power synthesis, timing, and physical design using RTL2GDS flows. The engineer will collaborate across global teams, define tool flows, and drive delivery of complex ICs. Candidates should have a bachelor’s or master’s in Electrical Engineering, 12–14+ years of RTL/ASIC experience, expertise in Verilog, SystemVerilog, CDC, synthesis, P&R, UPF, and scripting, and a proven track record of releasing high‑performance chips. Strong communication, cross‑functional collaboration, and leadership skills are essential. onsemi offers a dynamic environment focused on automotive, industrial, and consumer power solutions.

What you’ll do

• Perform trade‑off analysis between architecture options
• Benchmark platform components
• Define and deploy platform front‑end tool flow
• Design digital RTL, low‑power, synthesis, timing analysis
• Interface with physical design using RTL2GDS flows
• Collaborate with design architects, verification, PM, analog teams
• Implement micro‑architecture to RTL with feature refinement
• Develop and streamline methodology, coding, integration flows

What you’ll bring

• Bachelor's in Electrical Engineering or related, 14+ years experience
• Master's in Electrical Engineering, 12+ years RTL design experience
• Lead digital design, architecture, ASIC/mixed-signal chip development
• Expert in RTL, CDC, ASIC synthesis, timing, P&R, UPF, SystemVerilog
• Proficient in Verilog, TCL, Perl/Python/XML scripting
• Platform-based development experience
• Strong trade‑off analysis for power, performance, area
• Track record of delivering complex ICs to market
• Excellent communication and cross‑functional collaboration
• Experience with microprocessor interconnects and peripheral integration

Education

Bachelors