Senior Principal Engineer, RTL ASIC Design

About the role

Custom and Compute Solutions Business Unit at Marvell designs advanced SoCs. The Senior Principal Engineer, RTL ASIC Design defines architecture, micro‑architecture and register specs, implements RTL, collaborates with hardware, firmware and security teams, and leads verification and performance analysis. Hyderabad, on-site.

What you’ll do

• Define SoC and subsystem architecture and specifications
• Implement RTL designs following best practices
• Guide physical design teams on floorplanning, power analysis and timing sign‑off
• Partner with verification teams on test plans, simulation and emulation
• Coordinate with IP vendors to customize third‑party IPs
• Conduct performance and architectural reviews with cross‑functional stakeholders
• Develop and evaluate design and verification methodologies
• Collaborate with hardware, firmware and security teams to ensure design efficiency

What you’ll bring

• 18+ years ASIC/SoC design experience
• Expertise in RTL coding and verification
• Strong background in micro‑architecture and register specification
• Experience with high‑speed interconnects (PCIe, CXL, DDR)
• Proficiency in HDL and scripting languages
• Knowledge of ARM‑based SoC architectures and security
• Ability to perform trade‑off analysis (area, power, performance)
• Collaboration with cross‑functional global teams

Skills