Active listing
Design Verification Lead
About the role
Weekday AI client team focuses on delivering high‑quality semiconductor products through robust verification. The Design Verification Lead builds and maintains SystemVerilog/UVM environments, executes simulation‑based verification, and drives coverage closure for complex IP and SoC designs. Bengaluru, on-site, full‑time role with relocation assistance.
What you’ll do
- Develop verification plans from specifications
- Create reusable SV/UVM environments
- Execute functional and gate‑level simulations
- Automate regression flows and coverage analysis
- Integrate and validate third‑party verification IPs
- Debug design issues with architecture teams
- Participate in verification reviews and defect analysis
- Maintain verification milestones and quality standards
What you’ll bring
- 7+ years verification experience
- Strong SystemVerilog expertise
- UVM methodology proficiency
- Experience with PCIe, AXI, DDR protocols
- Simulation and gate‑level debugging
- Coverage analysis and closure
- Integration of third‑party VIPs
- Cross‑functional collaboration