Q
Hiring companyQualcomm
Verified 5 days ago
Low Power Design Engineer, Sr Lead
Bangalore, India Full-time On-site
About the role
Qualcomm Hardware Engineering team focuses on low power design for DSP IPs, ensuring efficient power consumption across complex SoCs. The Low Power Design Engineer leads power intent development, validation, and optimization using UPF, CLP, and PTPX, collaborating with synthesis and physical design teams. Bangalore, India, on-site role.
What you’ll do
- Create power specifications for DSP IPs
- Develop and validate power intent using UPF at RTL and gate level
- Project and track dynamic and leakage power across implementation stages
- Debug MV cell insertion issues and adjust UPF accordingly
- Collaborate with cross‑functional SOC and subsystem teams for power handoff
What you’ll bring
- 3+ years hardware engineering experience
- Hands‑on UPF development
- Power intent validation with CLP
- Power analysis using PTPX
- TCL or Perl scripting
- Dynamic and leakage power optimization
Skills
Power intentUPFCLPPTPXTCL scriptingPerl scriptingDynamic power analysisLeakage power optimization
Benefits
- Health insurance
- 401(k) matching
- Paid time off
- Employee stock purchase plan
Education
Bachelor's degree in Computer Science, Electrical/Electronics Engineering or related field