Senior Engineer, Low Power Design

About the role

Low-Power Physical Design team at Ericsson builds digital ASICs for 5G/6G networks. The Senior Engineer drives power estimation, analysis, and sign‑off using Synopsys PrimePower, collaborates with RTL, physical design, and architecture teams, and defines power‑closure methodology. Bangalore, India, on-site role with hybrid collaboration across global teams.

What you’ll do

• Own dynamic and leakage power analysis across design modes and PVT corners
• Generate and validate switching activity files (SAIF/VCD) for accurate power estimation
• Define workload scenarios and drive power optimization with RTL designers
• Coordinate IR drop analysis and address electromigration violations
• Define and own power sign‑off checklist and lead tape‑out readiness reviews
• Support synthesis teams with power‑aware optimization and review QoR results
• Contribute to STA reviews ensuring timing integrity after power optimizations
• Engage with EDA vendors to evaluate tool features and resolve issues

What you’ll bring

• 10+ years in power analysis or low‑power design
• Expert-level Synopsys PrimePower (PTPX) proficiency
• Experience with UPF/CPF multi‑voltage flows
• Familiarity with IR drop tools (RedHawk, VoltageStorm)
• Proficiency in Tcl; Python scripting a strong plus
• At least one tape‑out on 7nm or below

Skills

Education

B.Tech / M.Tech / M.S. in Electronics Engineering, VLSI Design, Computer Engineering or related field