Senior RTL Design Lead

About the role

Weekday AI Client team focuses on delivering high‑performance ASIC/SoC solutions for its customers. The Senior RTL Design Lead owns microarchitecture and RTL development of complex IPs, driving the full RTL lifecycle from specs to sign‑off while collaborating with verification, DFT, physical design and architecture teams. Based in Bengaluru, on‑site role with potential relocation assistance.

What you’ll do

• Lead RTL design and microarchitecture of complex IPs
• Develop synthesizable RTL meeting performance, power, area targets
• Conduct code reviews, lint analysis, CDC verification
• Collaborate with verification, DFT, physical design, STA teams
• Define and promote RTL coding standards and best practices
• Mentor junior engineers and provide technical guidance
• Support synthesis, timing closure, and design constraint development
• Drive continuous process improvements

What you’ll bring

• 5+ years ASIC/SoC RTL design
• Expertise in Verilog and SystemVerilog
• Microarchitecture development experience
• Proficiency with linting, CDC analysis, synthesis
• Familiarity with Synopsys Design Compiler, SpyGlass, PrimeTime
• Knowledge of AMBA/AXI, PCIe, DDR protocols
• Experience mentoring junior engineers
• Strong analytical and debugging skills