Senior Digital/RTL IC Design Engineer

About the role

Senior Digital/RTL IC Design Engineer at Omnidesigntech focuses on high‑performance ADC/DAC digital datapaths. The role requires deep RTL design, verification, and behavioral modeling expertise, along with support for synthesis, timing closure, and place‑and‑route flows in advanced CMOS processes. Candidates must master Verilog/SystemVerilog, mixed‑signal control loops, and Cadence toolsets (Genus, Tempus, Modus, Innovus, Encounter). Responsibilities include writing robust testbenches, automating design flows with scripting, and ensuring stringent timing and constraint compliance across multiple clock domains. The position demands a strong foundation in digital ASIC concepts, DSP, and analog backend integration, with a proven track record of delivering reliable, high‑speed digital controllers for cutting‑edge converters.

What you’ll do

• Design RTL for ADC/DAC digital datapaths
• Verify and model digital controllers
• Support synthesis and timing closure
• Assist P&R flow
• Write comprehensive testbenches
• Automate design flows via scripting
• Use Cadence toolsets for ASIC design
• Ensure multi‑clock domain constraints
• Perform static timing analysis
• Generate scan chain vectors

What you’ll bring

• 5+ years in high‑performance digital/mixed‑signal IC design
• Advanced CMOS process experience
• Strong Verilog RTL coding (state machines, adders, multipliers)
• Digital design for mixed‑signal control loops
• Behavioral Verilog (wreals)
• Cadence Genus, Tempus, Modus tool proficiency
• SystemVerilog and assertions
• Place & route flow with Innovus
• Digital signal processing (MATLAB)
• Synthesis and timing closure expertise

Skills

Education

Bachelor