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Hiring companyOmnidesigntech
Verified today
Senior Verification Engineer
Bangalore, Karnataka, India Full-time Hybrid
About the role
Senior Verification Engineer at Omnidesigntech responsible for designing and implementing verification architecture for SoC and subsystem levels. Leads creation of test plans, directed and random test cases, and coverage analysis using UVM/OVM/SystemVerilog. Works closely with RTL designers and system architects to translate specifications into verification requirements. Performs gate‑level simulation, debugging, and generates functional coverage reports. Requires strong scripting skills in Perl, Python, and Linux shells, and deep knowledge of ASIC simulation tools such as Verdi and Siloti.
What you’ll do
- Define verification strategies, methodologies, and simulation environments.
- Collaborate with RTL designers, architects, and verification engineers to develop requirements and test plans.
- Develop, maintain, and publish verification specifications.
- Analyze and debug simulation failures, generate coverage reports.
- Run gate‑level simulations and debug issues.
What you’ll bring
- BS in Electrical Engineering with 3+ years experience or MS with 1+ year.
- Proficient in ASIC simulation tools (Verdi, Siloti) and verification languages (UVM, OVM, SystemVerilog, Verilog, Vera).
- Experienced in writing test plans, directed and random test cases, and coverage analysis.
- Strong scripting skills in Perl, Python, and Linux shell environments.
Skills
Verification architecture designUVM/OVM/SystemVerilog testbench developmentCoverage analysis and reportingGate‑level simulation debuggingScripting (Perl, Python, Linux)
Education
Bachelor