CPU STA/Timing Engineer

About the role

Qualcomm India Private Limited seeks a CPU STA/Timing Engineer in Bangalore, India, to drive timing analysis and closure for high-performance CPU core and uncore designs. The role involves collaborating with microarchitecture, RTL, and physical design teams to meet aggressive frequency and power targets across block, cluster, and full-chip hierarchies. This is an on-site position focused on ensuring signoff quality through detailed timing verification and ECO implementation.

What you’ll do

• Drive timing analysis and closure for complex, multi-GHz CPU designs across block, cluster, and full-chip hierarchies
• Work closely with CPU microarchitecture, RTL, and DFT teams to define, implement, and validate timing constraints
• Perform STA for high-performance CPU designs at block, cluster, and SoC/top-level hierarchies across multiple modes, corners, and scenarios
• Analyze timing on frequency-critical CPU paths and collaborate with RTL and DFT teams to drive logic and micro-architectural fixes
• Provide actionable timing feedback to block-level and top-level physical design engineers to enable CPU frequency and timing closure
• Partner with CAD and methodology teams to develop, deploy, and enhance CPU-specific timing flows and infrastructure
• Generate and review timing ECOs (logic and physical) to close setup, hold, noise, and cross-talk violations in CPU designs
• Contribute to CPU timing methodology definition, best practices, and documentation for consistent signoff quality

What you’ll bring

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field
• 2+ years of Hardware Engineering or related work experience

Nice to have

• MS degree in Electrical Engineering with 3+ years of hands-on experience in STA and timing closure
• Strong experience with STA and timing closure for high-performance CPU or processor-class SoCs
• Expertise in multi-clock, multi-domain CPU designs with aggressive frequency targets
• Experience in deep sub-micron technology nodes and advanced process technologies
• Proven experience performing STA on large CPU/SoC designs with multi-scenario and signoff-quality closure
• Hands-on knowledge of timing ECO techniques and their implementation for CPU frequency closure
• Solid understanding of standard cell libraries, CPU-critical path optimization, and timing trade-offs
• Familiarity with circuit modeling, transistor fundamentals, and worst-case corner selection for CPU timing signoff

Skills

Education

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field