About the role

Qualcomm Hardware Engineering team drives next‑generation CPU core and uncore designs. The engineer leads timing analysis and closure across block, cluster and SoC hierarchies, collaborating with microarchitecture, RTL, DFT and CAD teams to meet aggressive frequency and power targets. Bangalore office, on‑site work model, relocation assistance available.

What you’ll do

Perform STA for block, cluster and top‑level CPU designs across modes and corners
Analyze critical paths and provide timing feedback to physical design teams
Generate and review timing ECOs to resolve setup, hold and noise violations
Partner with CAD and methodology teams to enhance timing flows
Document timing methodology and best practices

What you’ll bring

Bachelor's degree in Computer Science, Electrical/Electronics Engineering or related field
2+ years hardware engineering experience or Master's with 1+ year experience
PhD in related field acceptable

Nice to have

Experience with STA and timing closure for high‑performance CPUs
Proficiency in multi‑clock, multi‑domain timing flows
Knowledge of standard cell libraries and timing ECO techniques
Familiarity with Verilog and CPU/SoC architecture

Skills

STA timingCPU architectureTiming closureECO generationCAD toolsVerilogMulti‑clock designAdvanced process nodes

Benefits

Relocation assistance