Staff Design Verification Engineer, DSP/NPU

About the role

DSP team at Qualcomm designs high‑performance DSP/NPU cores for mobile, AI, and automotive SoCs. The Staff Design Verification Engineer leads verification of complex DSP IP, building SystemVerilog/UVM testbenches, developing methodologies, and ensuring coverage across IP, subsystem, and SoC levels. Bangalore office, on‑site work model, relocation assistance available.

What you’ll do

• Drive design verification of DSP IP with global architecture and implementation teams
• Implement and improve SystemVerilog/UVM testbench architecture
• Develop verification environments, test plans, and meet coverage goals
• Perform simulations, debug IP, subsystem, and SoC failures
• Conduct gate‑level simulation bring‑up and power‑aware verification
• Develop automation scripts and verification methodologies
• Collaborate with cross‑functional teams to ensure product quality

What you’ll bring

• 6+ years hardware engineering experience
• Proficiency in SystemVerilog/UVM testbench development
• Experience with verification methodologies, automation, and coverage goals
• Hands‑on simulation, debugging at IP and SoC levels
• Knowledge of power‑aware RTL verification and gate‑level simulation
• Scripting skills in Perl, Python, Shell
• Familiarity with Synopsys/Mentor/Cadence simulators
• Strong analytical and communication skills

Skills

Education

Bachelor's degree in Computer Science, Electrical/Electronics Engineering or related field