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Hiring companySiFive
Verified today
Senior Staff Engineer, Design Verification
Hyderabad, India Full-time On-site
About the role
Design Verification Team at SiFive focuses on ensuring correctness of complex out‑of‑order CPU cores. The Senior Staff Engineer leads verification strategy, builds SystemVerilog/UVM testbenches, defines coverage models and drives sign‑off for major core blocks while mentoring junior engineers. Hyderabad, India, on-site work model.
What you’ll do
- Own verification strategy and methodology for major core subsystems
- Architect and implement reusable UVM testbenches and stimulus generators
- Define coverage models, sign‑off criteria, and develop SVA assertions
- Lead debugging of complex out‑of‑order bugs and memory ordering issues
- Collaborate with micro‑architecture, RTL, performance, and post‑silicon teams
- Mentor junior and mid‑level verification engineers
What you’ll bring
5+ years verification experience
Nice to have
- Bachelor's or Master's in Engineering
- SystemVerilog/UVM expertise
- Out‑of‑order CPU architecture knowledge
- Coverage and assertion development skills
- Mentoring junior engineers
Skills
SystemVerilogUVMCPU verificationCoverage analysisAssertion developmentDebuggingMethodology developmentMentoring